Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all

Donckers, N., Dualibe, Fortunato Carlos Augusto ORCID: https://orcid.org/0000-0002-2889-315X and Verleysen, Michel ORCID: https://orcid.org/0000-0003-4366-6155 (1999) Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all. In: International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro, 7 al 9 de abril de 1999, Granada.

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Resumen

A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations. © 1999 IEEE.

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Documento de conferencia (Artículo)

DOI:

https://doi.org/10.1109/MN.1999.758887

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